1. Field of the Invention
The present invention relates to jitter test and, specifically, to a technique of jitter test in a communication system based on the OSI (Open Systems Interconnection) Reference Model.
2. Description of Related Art
The practical application of the OSI (Open Systems Interconnection) protocol is rapidly expanding as an international standard protocol architecture for multivendor connection, and various connection architectures based on the OSI Reference Model are standardized. Recently, the IEEE (Institute of Electrical and Electronics Engineers) 802.3 Working Group that develops standards for Ethernet (registered trademark), which is MAC (Media Access Control) that is the lower sublayer in Layer 2 (Data link layer) of the OSI Reference Model, defines 10 Gigabit Ethernet (10 GbE) with a data rate of ten times as fast as Gigabit Ethernet as the most recent Ethernet standard by IEEE802.3ae. The introduction of the 10 GbE standard is proceeding in the fields of LAN (Local Area Network)/MAN (Metropolitan Area Network) in addition to backbone networks of communication common carriers.
A scheme of data transmission and receipt in communication equipment at the 10 GbE data rate is described hereinafter.
FIG. 5 is a schematic view of a transmitting end. In a MAC (Media Access Control) layer 14, a MAC frame is generated by adding a synchronizing signal, a CRC (Cyclic Redundancy Check), a minimum packet interval and so on to frame data that is supplied from an upper layer 12.
The MAC frame that is obtained in the MAC layer 14 is output to a PCS (Physical Coding Sublayer) 16. The PCS 16 includes an encoding function 17 and encodes the MAC frame. The MAC frame that is encoded by the PCS 16 is output to a communication line via a physical layer.
FIG. 6 is a schematic view of a receiving end. In the receiving end, the MAC frame that is transmitted through the communication line is decoded by a decoding function 27 of a PCS 26 and output to a MAC layer 24. In the MAC layer 24, a payload portion that is contained in the MAC frame is extracted from the decoded MAC frame. The extracted payload is supplied to an upper layer 22 and processed therein.
When building a communication system, it is necessary to perform various end-to-end tests. The IEEE802.3ae standard specifies various end-to-end capability evaluation tests, which includes jitter test. In the jitter test, a transmitting end generates a jitter test pattern and outputs it to a communication line, and a receiving end compares the received jitter test pattern which is transmitted through the communication line with the original jitter test pattern, which is the one before being transmitted. Based on the comparison result, the jitter performance of a system is evaluated. The format in the transmission of a jitter test pattern is specified as a MAC frame format by the IEEE802.3ae standard.
A 10 GbE jitter test system is disclosed in Lattice Semiconductor Corporation, “10 Gb Ethernet XGXS IP Core”, April 2004, pp. 4-6, pp. 11-13. In this system, a PCS circuit at a transmitting end includes a jitter test pattern generation circuit, and a PCS circuit at a receiving end includes a jitter test pattern verification circuit. During the jitter test, the jitter test pattern generation circuit in the PCS circuit at the transmitting end generates a jitter test pattern and outputs it. The jitter test pattern verification circuit in the PCS circuit at the receiving end compares the received jitter test pattern with the original jitter test pattern. The jitter performance of the system is evaluated based on the comparison result.
The jitter test system that is disclosed in the above document is described hereinafter with reference to FIG. 7.
FIG. 7 is a view schematically showing the jitter test system that is disclosed in the above document. The jitter test system 50 includes a transmitting-end upper circuit 31, a transmitting-end MAC circuit 32, and a transmitting-end PCS circuit 33 as a transmitting end, and also includes a receiving-end PCS circuit 43, a receiving-end MAC circuit 42, and a receiving-end upper circuit 41 as a receiving end. The transmitting-end MAC circuit 32 and the receiving-end MAC circuit 42 perform processing in a MAC layer, and the transmitting-end upper circuit 31 and the receiving-end upper circuit 41 perform processing in an upper layer than MAC.
The transmitting-end MAC circuit 32 generates a MAC frame with the use of data from the transmitting-end upper circuit 31.
The transmitting-end PCS circuit 33 includes a test pattern generation circuit 34, a selector circuit 35, and an encoder circuit 36.
When performing jitter test, a test indication signal that indicates jitter test is transmitted to the test pattern generation circuit 34, the selector circuit 35, and a test pattern verification circuit 44. In response to the test indication signal, the test pattern generation circuit 34 generates a jitter test pattern. Although the selector circuit 35 normally supplies an output of the transmitting-end MAC circuit 32 to the encoder circuit 36, it supplies an output of the test pattern generation circuit 34 to the encoder circuit 36 when it has received the test indication signal.
Because data should be in the MAC frame format when it is output to a communication line, the test pattern generation circuit 34 generates a jitter test pattern in the MAC frame format by adding the portions of a synchronizing signal, a CRC and a minimum packet interval to a main body of a jitter test pattern.
The transmitting-end PCS circuit 33 encodes the MAC frame (frame data or a frame that contains a jitter test pattern body as a payload) that is output from the selector circuit 35 using the encoder circuit 36 and then outputs the encoded MAC frame.
The receiving-end PCS circuit 43 includes a decoder circuit 46 and the test pattern verification circuit 44. The decoder circuit 46 decodes the MAC frame that is transmitted through a communication line and outputs it to the receiving-end MAC circuit 42 and the test pattern verification circuit 44. The receiving-end MAC circuit 42 extracts a payload from the MAC frame that is decoded by the decoder circuit 46 and outputs it to the receiving-end upper circuit 41. The receiving-end upper circuit 41 performs upper processing on the received data.
The test pattern verification circuit 44 performs verification of a jitter test pattern on the MAC frame (which is a MAC frame that contains a main body of a jitter test pattern as a payload in this example) that is output from the decoder circuit 46 when it has received the test indication signal. The verification result of the test pattern verification circuit 44 is used for the evaluation of the jitter performance of the system.
As described above, in the jitter test system 50 shown in FIG. 7, the test pattern generation circuit 34 needs to generate a jitter test pattern in the MAC frame format. Therefore, the test pattern generation circuit 34 needs to generate the synchronizing signal, CRC and minimum packet interval portions, and thus needs to include a circuit for the generation, which causes a circuit size of the test pattern generation circuit 34 to be large. Further, in the receiving end also, the test pattern verification circuit 44 needs to verify the synchronizing signal, CRC and minimum packet interval portions as well, which causes a circuit size of the test pattern verification circuit 44 to be large.
The IEEE802.3ae standard specifies to perform jitter test, and further specifies a jitter test pattern. The jitter test pattern generation circuit and verification circuit that are specified by such a standard should be configured as above.